Delay-Aware Plug-and-Play Residual Capacity / delay_controller.py

Mechanism confirmed, baseline not beaten

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 1"""Delay-aware admissibility rule for attachable residual modules."""
 2import math
 3
 4def critical_delay(a, gain):
 5    if gain <= a:
 6        return math.inf
 7    return math.acos(-a / gain) / math.sqrt(gain * gain - a * a)
 8
 9def max_admissible_gain(a, delay):
10    if delay <= 0:
11        return math.inf
12    lo, hi = a * (1 + 1e-12), max(2 * a, a + 1 / delay)
13    while critical_delay(a, hi) > delay:
14        hi *= 2
15    for _ in range(100):
16        mid = (lo + hi) / 2
17        if critical_delay(a, mid) > delay:
18            lo = mid
19        else:
20            hi = mid
21    return (lo + hi) / 2
22
23def select_modules(gains, benefits, a, delay, minimum_gain=0.0):
24    limit = max_admissible_gain(a, delay)
25    order = sorted(range(len(gains)), key=lambda i: benefits[i] / max(gains[i], 1e-12), reverse=True)
26    chosen, total = [], 0.0
27    for i in order:
28        if total + gains[i] < limit:
29            chosen.append(i); total += gains[i]
30    if total < minimum_gain:
31        return [], 0.0, limit
32    return chosen, total, limit